Clock control circuit and method

ABSTRACT

A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit  10  is fed with clocks from a position on a forward route  11   1  of a direction-reversed clock propagation path, adapted for being fed with input clocks at its one end, and from a position on a return route  11   2  corresponding to the position on the forward route  11   1 . The timing difference between these clocks is averaged to output an averaged timing difference.

FIELD OF THE INVENTION

[0001] This invention relates to a clock controlling circuit and a clockcontrolling method. More particularly, it relates to a clock controllingcircuit and a clock controlling method usable with advantage in a clocksupplying circuit of a semiconductor integrated circuit having a circuitsynchronized with system clocks.

BACKGROUND OF THE INVENTION

[0002] In a semiconductor integrated circuit controlling the internalcircuit in synchronism with system clocks, preset circuit operations areexecuted each clock period to control the internal circuit in itsentirety. Recently, the chip size is increased in keeping pace with thetendency towards the increasing degree of integration and towards thehigher function of the function of the semiconductor integrated circuit.On the other hand, as the clock period becomes shorter with theincreasing operating frequency, the shortening of the delay timedifference in the clock path is presenting problems.

[0003] In order to cope with this task, there is disclosed in, forexample, the JP Patent Kokai JP-A-9-258841 a clock supplying method inwhich there are provided an oncoming clock line and an outgoing clockline, these clock lines are divided into two lines of forward and returnpaths, and in which the wiring delay is detected to adjust clocks. Thereis disclosed a configuration comprising a receiver having first andsecond input terminals at a first position on the forward path and asecond position near the first position on the forward path,respectively. The delay in the forward path and return path is detectedfrom these first and second input terminals to output an average valueof the delay caused in the forward and return paths.

[0004] That is, in the JP Patent Kokai JP-A-9-258841, a point A of aforward route 111, as an input, is coupled to an end of a phasedetection circuit 181 through a variable delay line 171 and a variabledelay line 172, a point H of a return route 112, as an input, is coupledto the other end of the phase detection circuit 181, the delay time ofthe variable delay lines 171, 172 is variably controlled for phaseadjustment, and an output of a receiver is derived from a junction pointof the variable delay lines 171, 172.

[0005] Since the delay time from the point A of the forward route 111 ofthe clock propagation path up to a turning point 113 is a, the delaytime from the point A to the point H is 2a, an average value of thedelay time between the points A and H is a, the delay time from thepoint b of the forward route 111 of the clock transmitting line to theturning point 113 is b and the delay time from the point B to the pointG is 2b. So, the sum of the delay time (a−b) from the input end to thepoint b and the delay time ((a−b)+(a−b)+2b) from the input end to thepoint G is |(a−b)+((a−b)+(a−b)+2b)|is 2a, with an average value being a.In this manner, clock signals with the corresponding phase can beobtained without dependency on the positions of the clock propagationpath.

[0006] In this manner, in the conventional method disclosed in the JPPatent Kokai JP-A-9-258841, a clock path is direction-reversed and adelay timing of an intermediate point between the forward and returnroutes is taken to adjust the delay amount of the variable delay line inthe clock path.

[0007] For adjusting the delay in this manner, a feedback circuit loop,exemplified by a phase locked loop (PLL) or a delay lock loop (DLL), inwhich the phase difference is detected by a phase detection circuit andthe delay caused in the variable delay line is varied based on thedetected phase difference, is routinely used.

SUMMARY OF THE DISCLOSURE

[0008] However, the PLL or DLL, constituting a feedback circuit,presents a problem that a period longer by about hundreds to thousandsof cycles is needed until clock stabilization is achieved.

[0009] There is also raised a problem that plural sets of the phasecomparators and delay circuit lines are needed thus increasing thecircuit scale.

[0010] In view of the aforementioned problems, it is an object of thepresent invention to provide a clock controlling circuit and a clockcontrol method for a circuit for eliminating the delay difference in theentire clock transmitting line, according to which the delay differencemay be eliminated in a shorter time than the case where the PLL circuitor the DLL circuit is used.

[0011] It is another object of the present invention to provide a clockcontrolling circuit and a clock control method according to which aphase comparator may be eliminated to prevent the circuit scale fromincreasing.

[0012] According to a first aspect of the present invention, there isprovided a clock controlling circuit comprising:

[0013] a timing difference dividing circuit for receiving a clock at afirst position on a forward route of a clock propagation pathdirection-reversing input clocks fed at one end thereof, and a clock ata second position on a return route thereof corresponding to the firstposition on the forward route,

[0014] the timing difference dividing circuit outputting a signal of adelay time corresponding to a time obtained on dividing a timingdifference of the two clocks by a preset interior division ratio.

[0015] According to a second aspect of the present invention, there isprovided a clock controlling circuit comprising:

[0016] a timing difference averaging circuit for receiving a clock at afirst position on a forward route of a clock propagation pathdirection-reversing input clocks fed at one end thereof, and a clock ata second position on a return route thereof corresponding to the firstposition on the forward route,

[0017] the timing difference dividing circuit outputting a signal of adelay time corresponding to a time obtained on evenly dividing a timingdifference of the two clocks.

[0018] According to a third aspect of the present invention, the timingaveraging circuit is configured to issue an output signal with a delaytime equal to the sum of a first delay time until output signal isissued after one of the two input clocks undergoing transition at anearlier time point is input simultaneously to first and second inputsadapted for being fed with the two clocks and a second delay timecorresponding to a time (T/2) obtained on dividing the timing differenceT of said two clocks into two equal portions.

[0019] According to a fourth aspect of the present invention, there isprovided a timing averaging circuit fed with clocks from a firstposition on a forward route of a clock propagation path, adapted fordirection-reversing clocks frequency divided by a frequency dividingcircuit and input at an end of the clock propagation path and from asecond position on a return route thereof corresponding to the firstposition on the forward route, and a multiplication circuit formultiplying an output of the timing averaging circuit.

[0020] According to a fifth aspect of the present invention, there isprovided a clock controlling circuit comprising:

[0021] a timing averaging circuit provided with a frequency dividingfunction for frequency dividing two, first and second, clocks, i.e., thefirst clock from a first position on a forward route of a clockpropagation path fed with input clocks at one end anddirection-reversing the input clocks and the second clock from a secondposition corresponding to the first position to generate frequencydivided multi-phase clocks of plural different phases,

[0022] the timing averaging circuit outputting a signal of a delay timecorresponding to a time equally dividing a timing difference betweenfrequency divided clocks having a corresponding phase among clocksignals obtained on frequency division of the two clocks; and

[0023] a synthesis circuit for synthesizing plural outputs of the timingaveraging circuits into one signal and for outputting the one signal.

[0024] According to a sixth aspect of the present invention, there isprovided a clock controlling method, averages the timing difference ofclocks taken from a first position on a forward route of a clockpropagation path fed with input clocks at one end anddirection-reversing the input clocks and from a second position on areturn route corresponding to the first position on the forward route togenerate a clock or clocks with matched clock timing irrespective of theclock taking positions on the forward and return route.

[0025] Other aspects and features of the present invention are disclosedalso in the claims, the entire disclosure thereof being incorporatedherein by reference thereto.

BRIEF DESCRIPTION OF THE DRAWINGS

[0026]FIG. 1 shows the structure of an embodiment of the presentinvention.

[0027]FIG. 2 is a timing chart for illustrating the operation of theembodiment of the present invention.

[0028]FIG. 3 shows the structure of a timing averaging circuit embodyingthe present invention.

[0029]FIG. 4 shows the operation of a timing averaging circuit embodyingthe present invention.

[0030]FIG. 5 shows the structure of a second embodiment of the presentinvention.

[0031]FIG. 6 shows the structure of another exemplary timing averagingcircuit embodying the present invention.

[0032]FIG. 7 shows the structure of another exemplary timing averagingcircuit embodying the present invention.

[0033]FIG. 8 shows the structure of another exemplary timing averagingcircuit embodying the present invention.

[0034]FIG. 9 shows the structure of a third embodiment of the presentinvention.

[0035]FIG. 10 is a timing chart for illustrating the operation of thethird embodiment of the present invention.

[0036]FIG. 11 shows an exemplary structure of a multiplication circuitof the third embodiment of the present invention.

[0037]FIG. 12 shows an exemplary structure of a multi-phase clockmultiplication circuit shown in FIG. 11.

[0038]FIG. 13 shows an illustrative structure of the multi-phase clockmultiplication circuit.

[0039]FIG. 14 is a timing chart for illustrating the operation of themulti-phase clock multiplication circuit.

[0040]FIG. 15 shows an illustrative structure of timing differencedividing circuits 208, 209 of a four-phase clock multiplication circuitof FIG. 13.

[0041]FIG. 16 shows a structure of a fourth embodiment of the presentinvention.

[0042]FIG. 17 shows a structure of a timing averaging circuit providedwith a frequency dividing function.

[0043]FIG. 18 is a timing chart for illustrating the operation of thefourth embodiment of the present invention.

[0044]FIG. 19 shows a structure of a fifth embodiment of the presentinvention.

[0045]FIG. 20 is a timing chart for illustrating the operation of thefifth embodiment of the present invention.

[0046]FIG. 21 shows a structure of the fifth embodiment of the presentinvention.

[0047]FIG. 22 shows an exemplary structure of a conventional clockcontrolling circuit.

PREFERRED EMBODIMENTS OF THE INVENTION

[0048] A preferred embodiment of the present invention is explained. Inits preferred embodiment, shown in FIG. 1, the present inventionincludes a timing averaging circuit which is fed with clocks from afirst position on a forward route of a clock propagation path adaptedfor being fed with input clocks at one end and direction-reversing theinput clocks and from a second position on a return route correspondingto the first position on the forward route and which divides the timingdifference of these clocks into two equal portions to output theresulting clocks. The delay time between the first position and thedirection-reversing point 11 ₃ of the clock propagation path is equal tothe delay time between the direction-reversing point 11 ₃ of the clockpropagation path and the second position.

[0049] The timing averaging circuit issues an output signal with a delaytime equal to the sum of a (first) delay time (Cons) until outputting ofan output signal after one of the two input clocks undergoing transitionat an earlier time is input simultaneously to the first and second inputends fed with the two clocks and a (second) delay time corresponding toa time (T/2) obtained on dividing the timing difference T of the twoclocks into two equal portions. Namely, the present invention does notuse PLL, nor DLL. The timing averaging circuit is configured so that theinternal node is charged or discharged, based on one of two input clocksthat undergoes an earlier transition and so that the internal load ischarged or discharged based on the other clock undergoing be latertransition and the aforementioned one clock. The internal node isconnected to the input end. There is provided an inverting ornon-inverting buffer circuit an output logical value of which is changedwhen the internal node voltage becomes higher or lower than a thresholdvoltage.

[0050] In its preferred embodiment of the present invention, shown inFIG. 5, input clocks are input from one end of a clock propagation pathand branches to first and second forward routes (11A, 11B), with thefirst and second forward routes being direction-reversed (preferably, ina crossing fashion) on an opposite end to the said one end, with thereturn routes (11C, 11D) of the first and second routes thusdirection-reversed being arranged along the forward routes (11A, 11B) ofthe second and first routes. The clock controlling circuit includestiming averaging circuits 10 ₁, 10 ₂ for being fed with a clock fromfirst positions (A, B) on the forward route 11A of the first route andwith a clock from the second position (C, D) on the return route 11D ofthe second route for outputting a signal of delay time corresponding tothe time averaging a timing difference between the clocks in two equalportions, and timing averaging circuits 10 ₄, 10 ₃ for being fed withclocks from third positions E, F on a forward route 11 b of the secondroute and from fourth positions D, C on the return route 11C of thesecond route to average out the timing difference of these clocks tooutput the resulting clocks.

[0051] In a preferred embodiment of the present invention, shown in FIG.9, there are provided a frequency dividing circuit 14 for frequencydividing input clocks, timing averaging circuits 10 ₁, 10 ₂, 10 ₃, 10 ₄for being fed with clocks from first positions A, B, C and D on aforward route of a clock propagation path adapted for being fed withclocks frequency divided by the frequency dividing circuit, the pathdirection-reversing the clocks, and second positions H, G, E and F on areturn route corresponding to the first position on the forward route,the timing averaging circuit outputting a signal of a delay timecorresponding to a time dividing a timing difference of these clocks intwo equal portions, and multiplication circuits 15 ₁, 15 ₂, 15 ₃, 15 ₄for multiplying an output signal from the timing averaging circuits 10₁, 10 ₂, 10 ₃, 10 ₄ and outputting a multiplied output signal.

[0052] In a preferred embodiment of the present invention, shown in FIG.16, there are provided timing averaging circuits provided with frequencydividing functions (function units) 100 ₁ to 100 ₄ fed with two clocksfrom first positions A, B, C and D on a forward route 11 ₁ of the clockpropagation path and from second positions H, G, F, E corresponding tothe first positions on the forward route, and synthesis circuits 16 ₁ to16 ₄ for synthesizing plural outputs (L1 to L4, K1 to k4, J1 to J4 andI1 to I4) of the timing averaging circuits provided with the frequencydividing function 100 ₁ to 100 ₄ into one signal and for outputting theone signal.

[0053] The timing averaging circuit provided with the frequency dividingfunction has first and second frequency dividing circuits 101 ₁, 101 ₂for frequency dividing two clocks to output plural frequency dividedclocks having respective different phases, a plurality of timingaveraging circuits 102 ₁ to 102 ₄ for being fed with two frequencydivided clocks of the first and the second frequency dividing circuitshaving corresponding phases and a synthesis circuit 16 for synthesizingplural outputs L1 to L4 of the timing averaging circuits 102 ₁ to 102 ₄into one signal.

[0054] In a preferred embodiment of the present invention, shown in FIG.19, there are provided a frequency dividing circuit 14A for frequencydividing input clocks for outputting frequency divided clocks of pluraldifferent phases, a plurality of clock propagation paths 11-1 to 11-4for being fed at one end with a plurality of frequency divided clocksoutput from the frequency dividing circuit, a plurality of timingaveraging circuits (four TMs) for being fed with two clocks from a firstposition on the forward route and from a second position on a returnroute associated with the first position, for each of the plural clockpropagation paths, to output signals of delay time corresponding to thetime resulting from division of a timing difference of the two clocksinto two equal portions, and a synthesis circuit 16 for synthesizingplural outputs of the plural timing averaging circuits (four TMs).

[0055] In a preferred embodiment of the present invention, shown in FIG.21, there are provided timing averaging circuits 110 ₁ to 110 ₄ forbeing fed with two clocks from first positions A to D on a forward routeof a clock propagation path 111, and from second positions H, G, F and Eon the return route corresponding to the position on the forward route,and timing averaging circuits 120 ₁ to 120 ₄ for being fed with twoclocks from a certain position on the forward route of the second clockpropagation path 114 ₁, and from a position on the return routecorresponding to the position on the forward route.

[0056] There are also provided timing averaging circuits 121 ₁ to 121 ₄for being fed with two clocks from a certain position on a forward routeof a second clock propagation path 114 ₂, fed with clocks output fromthe timing averaging circuits 110 ₂ at one end for direction-reversingthe clocks and from a position on the return route corresponding to theposition on the forward route, timing averaging circuits 122 ₁ to 122 ₄for being fed with two clocks from a certain position on a forward routeof a second clock propagation path 114 ₃, fed with clocks output fromthe timing averaging circuits 110 ₃ at one end for direction-reversingthe clocks, and from a position on the return route corresponding to theposition on the forward route, and timing averaging circuits 123 ₁ to123 ₄ for being fed with two clocks from a certain position on a forwardroute of a second clock propagation path 114 ₄, and from a position onthe return route corresponding to the position on the forward route. Theoutput signals of these timing averaging circuits are arranged e.g., ina mesh-like fashion on a two-dimensional plane of a semiconductorintegrated circuit or a printed wiring board.

[0057] A few circuit configurations of the timing averaging circuits arehereinafter explained. The timing averaging circuit in a preferredembodiment of the present invention for being fed with clocks on forwardand return routes of the direction-reversing type clock propagationpath, shown in FIG. 3, includes first and second switch elements MP1,MP2 connected in parallel across the first power source and an internalnode and which are turned on and off when the first and second inputsIN1, IN2 are at first and second values, respectively, a third switchelement MN1 connected across the internal node N1 and a second powersource GND, the third switch element being fed on a control terminalwith an output of a logic circuit NOR fed with the first and secondinputs, and being turned on when the first and second inputs are at thesecond value, a capacitance C connected across the internal node N1 anda second power source GND and a buffer circuit BUT an output logicalvalue of which is determined based on the relative magnitudes of thepotential of the internal node N1 and the threshold value.

[0058] In a preferred embodiment of the present invention, shown in FIG.6, the timing averaging circuit includes a plurality of first switchelements MP1, MP2 connected in series across a first power source VCCand an internal node N52, the timing averaging circuit having itscontrol terminal fed with a first input IN1 and being turned off whenthe first input IN1 is at a first value, a plurality of second switchelements MN51, MN52 connected in series across the internal node N52 anda second power source GND, each second switch element having its controlterminal connected to the first input IN1 and being turned on when thefirst input IN1 is at a first value, a third switch element MP53connected in series across the first power source and a second powersource N52, the fourth switch element having its control terminalconnected to the first input IN1, and being turned off when the firstinput IN1 is at a first value, a fourth switch element MP54 having itscontrol terminal connected to the second input IN2 and being turned offwhen the second input IN2 is at a first value, a fifth switch elementMN54 connected in series across the internal node N52 and the secondpower source, the fifth switch element having its control terminalconnected to the first input, and being turned on when the first inputis at a first value, and a sixth switch element MN53 having its controlterminal connected to the second input and being turned on when thesecond input is at the first value and an inverter circuit INV51 anoutput logical value of which is determined based on the relativemagnitudes of the internal node and a threshold value. The switchelements MP55, MP56, control terminals which are connected to the secondinput, are connected to the first power source, the switching elementsMN55 MN56, control terminals which are connected to the second input,are connected to the second power source and the numbers of the switchelements operating as loads for the first and second inputs are equaleach other.

[0059] In a preferred embodiment of the present invention, shown in FIG.7, the timing averaging circuit includes a first switch element MP61connected across the first power source VCC and a first internal nodeN71, a first logical circuit NAND 61 fed with first and second inputsignals IN1, IN2 from an input end and having its output end connectedto a control terminal of the first switch element MP61, the first switchelement being turned on when both the first and second input signals areat a first value, a second switch element MN61 connected in seriesacross the first internal node N71 and the second power source GND andbeing turned off or on when the first input signal is at the first orsecond value, respectively, a third switch element MN62 turned on or offwhen an output signal OUT is at the first or second value, respectively,a fourth switch element MN63 connected in series across the firstinternal node N71 and the second power source and being turned off or onwhen the first input signal is at the first or second value,respectively, a fifth switch element MN64 turned on or off when anoutput signal OUT is at the first or second value, respectively, and asixth switch element MP66 connected across the first power source and athird internal node N73 for inputting the first internal node N71 to acontrol terminal.

[0060] The timing averaging circuit also includes a seventh switchelement MN65 connected across the second power source GND and the secondinternal node N72,

[0061] a second logical circuit NOR61 fed with first and second inputsignals IN1, IN2 and having its output end connected to a controlterminal of the seventh switch element MN65, the seventh switch elementMN65 being turned on when both the first and second input signals IN1,IN2 are at a second value, an eighth switch element MP64 connected inseries across the second internal node N72 and the first power sourceVCC and being turned on or off when the first input signal is at thefirst or second value, respectively, a ninth switch element MP62 turnedoff or on when an output signal is at the first or second value,respectively, a tenth switch element MP65 connected in series across thesecond internal node N72 and the first power source VCC and being turnedon and on when the second input signal is at the first or second value,respectively, an eleventh switch element turned off or on when theoutput signal is at the first or second value, respectively, a twelfthswitch element MP63 connected across the second power source and thethird internal node for inputting the second internal node to a controlterminal and an inverter circuit INV65 having its input terminal fedwith the third internal node and an output logical value of which isdetermined by the relative magnitudes of the third internal nodepotential and a threshold value. The clock control circuit furtherincludes circuit means for on/off controlling a first switch elementpair made up of the third switch element MN65 and the fifth switchelement MN64 and a second switch element pair made up of the ninthswitch element MP62 and the eleventh switch element MP63.

[0062] The circuit means may, for example, be buffer circuits INV67,INV66 for generating normal signals of an output signal prescribed bythe first and second input signals IN1, IN2. An output of the buffercircuit is connected in common to control terminals of the fifth switchelement MN65, fifth switch element MN64, ninth switch element MP62 andthe eleventh switch element MP63.

[0063] In a preferred embodiment of the present invention, shown in FIG.8, the timing averaging circuit includes a first switch element MP71connected across the first power source and a first internal node N81, afirst logical circuit NAND71 fed with first and second input signals andhaving its output end connected to a control terminal of the firstswitch element MP71, the first switch element MP71 being turned on whenboth the first and second input signals are at a first value, second andthird switch elements MN71, MN72 connected in series across the firstinternal node N81 and the second power source, with the second switchelement MN71 being turned off or on when the first input signal is atthe first or second value, respectively. The timing averaging circuitalso includes a sixth switch element MP76 connected across the firstpower source and a third internal node N83 for inputting the firstinternal node N81 to a control terminal.

[0064] The timing averaging circuit also includes a seventh switchelement MN75 connected across the second power source GND and the secondinternal node N82, a second logical circuit NOR71 fed with first andsecond input signals IN1, IN2 and having its output end connected to acontrol terminal of the eleventh switch element MP72, MP73, the seventhswitch element being turned on when both the first and second inputsignals are at a second value, eighth and ninth switch elements MP74,MP72 connected in series across the second internal node N82 and thefirst power source and being turned on or off when the first inputsignal is at the first or second value, respectively, a ninth switchelement turned off or on when an output signal is at the first or secondvalue, respectively, tenth and eleventh switch elements MP75, MP73connected in series across the second internal node N82 and the firstpower source and being turned on or off when the first input signal isat the first or second value, respectively, a twelfth switch elementMN76 connected across the second power source and the third internalnode N83 for inputting the second internal node to a control terminaland an inverter circuit INV75 having its input terminal fed with thethird internal node N83 and an output logical value of which isdetermined by the relative magnitudes of the third internal nodepotential and a threshold value.

[0065] An output of the first logical circuit NAND71 is connected incommon to control terminals of the ninth switch element MP72 and theeleventh switch element MP73, whilst an output of the second logicalcircuit NOR71 is connected in common to control terminals of the thirdswitch element MN72 and the fifth switch element MN73.

[0066] In a preferred embodiment of the present invention, shown in FIG.11, the structure of multiplication circuits 15 ₁ to 15 ₄ includes afrequency dividing circuit 2 for frequency dividing input clocks forgenerating and outputting plural clocks of different phases (multi-phaseclocks), a period detection circuit 6 for detecting the period of theinput clocks, and a multi-phase clock multiplication circuit 5 fed withmulti-phase clocks output from the frequency dividing circuit forgenerating the multi-phase clocks as multiplied clocks. The multi-phaseclock multiplication circuit includes a plurality of timing differencedividing circuits 4 a outputting signals corresponding to the dividedtiming difference between two inputs and a plurality of multiplicationcircuits 4 b for multiplying and outputting outputs of two the timingdifference dividing circuits. The plural timing difference dividingcircuits includes a timing difference dividing circuit fed with the samephase clocks and a timing difference dividing circuit fed with outputsof two the timing difference dividing circuits.

[0067] In a preferred embodiment of the present invention, shown in FIG.13, there are provided 2n timing difference dividing circuits foroutputting signals obtained on dividing the timing difference of twoinput timings, the 2i-1st timing difference dividing circuit 208, 210,212, 214, where 1≦i≦n, is fed with an ith same clock as the two inputs,the 2ith timing difference dividing circuit (209, 211, 213, 215), where1≦i≦n, is fed with the ith clock and (i+1 mod n)th clock, where moddenotes a remainder operation such that i+1 mod n means a remainderobtained on dividing I+1 with n, there being further provided 2n pulsewidth correction circuits 216 to 223 fed with an output of a Jth timingdifference dividing circuit, where 1≦J≦2n, and with an output of atiming difference dividing circuit, as input, where J+2 mod n means aremainder resulting from division of J+2 by n, and n multiplicationcircuits 224 to 227 fed with an output of a Kth pulse width correctioncircuit, where 1≦K≦n, and an output of the (K+n)th pulse widthcorrection circuit, as inputs.

[0068] In a preferred embodiment of the present invention, shown in FIG.15, the timing difference dividing circuit includes a logical circuitNOR14 fed as input with first and second input signals and which setsthe internal node to the potential of a first power source when thefirst and second input signals are at a first value, and a buffercircuit or an inverter circuit INV15 for changing the output logicalvalue depending on the relative magnitudes of the potential of theinternal node as an output of the logical circuit and a threshold value,a plurality of series connected switch elements and capacitances areconnected in parallel across the internal node and the second powersource (MN51 and CAP51, MN52 and CAP52, and MN53 and CAP53). Thecapacitance to be added to the internal node being determined by periodcontrol signal coupled to a control terminal of the switch.

[0069] By providing a semiconductor integrated circuit with the clockcontrol circuit according to the present invention, for supplying clocksto a clock synchronization circuit, phase-matched clocks can be suppliedover the entire clock propagation path.

[0070] For explanation of the above-described embodiments of the presentinvention in more detail, certain preferred embodiments of the presentinvention will be hereinafter explained with reference to the drawings.

[0071]FIG. 1 shows a structure of a preferred embodiment of the presentinvention. In the preferred embodiment of the present invention, shownin FIG. 1, a circuit comprised of a clock propagation path, folded onitself to constitute a forward route and a return route in which thetiming at a mid point of the forward and return routes is taken toadjust the delay induced in the clock path, includes a timing averagingcircuit for averaging the timing difference between respective pulses ofthe clock signals.

[0072] On the forward route 11 ₁ of the clock propagation path, thedelay time from a point A to a reversing point 11 ₃ is a, the delay timefrom a point B to the reversing point 11 ₃ is b, the delay time from apoint C to the reversing point 11 ₃ is c, and the delay time from apoint D to the reversing point 11 ₃ is d. On the return route 11 ₂ ofthe clock propagation path, a point E is at the delay time d fromreversing point 11 ₃, a point F is at the delay time c from reversingpoint 11 ₃, a point G is at the delay time b from reversing point 11 ₃,and a point H is at the delay time a from reversing point 11 ₃.

[0073] The clocks input from an input buffer 12 to the forward route 11₁ of the clock propagation path is turned back (direction-reversed) atthe reversing point 11 ₃ and propagate on the return route 112. Twoclock signals at points A and H are input to a timing averaging circuit10 ₁, from which an output signal L, as an average of the two timingdifferences, is output. Similarly, two clock signals at points B and Gare input to a timing averaging circuit 10 ₂, from which an outputsignal L, as an average of the two timing differences, is output. Twoclock signals at points G and F are input to a timing averaging circuit10 ₃, from which an output signal J, as an average of the two timingdifferences, is output. Similarly, two clock signals at points D and Eare input to a timing averaging circuit 10 ₄, from which an outputsignal I, as an average of the two timing differences, is output.

[0074]FIG. 2 shows a timing diagram for illustrating the basic operationof an embodiment of the present invention shown in FIG. 1. The clockpropagation path is arranged in a turned-back fashion, as shown inFIG. 1. The respective points A, B, C and D of the forward route 11 ₁are adjacent to respective points H, G, F and E of the return route 11₂. Clock outputs are input to timing averaging circuits 10 ₁ to 10 ₄which then output four timing difference signals each having a medianvalue between two clocks.

[0075] Since the median values of the timing signals 2 a, 2 b, 2 c and 2d at the respective neighboring points A-H, B-G, C-F and D-E are equalto the timing at the reversing-back point 11 ₃, the output timings ofoutputs I, J, K and L of the timing averaging circuits become equal oneanother.

[0076] That is, referring to FIG. 2, the timing of a failing edge of anoutput L of a timing averaging circuit 10 ₁ outputting an average valueof the timing difference 2a of the adjacent point set A-H is (presetdelay time Cons)+(2a/2)=Cons+a, with respect to the rising edge of theclock at point A. The preset delay time cons is the propagation delaytime proper to e.g., the timing averaging circuits 10 ₁ to 10 ₄.Specifically, the preset delay time cons is the propagation delay timefrom inputting a given signal to two inputs of the timing averagingcircuit until outputting of the resulting output signal.

[0077] An output K of a timing averaging circuit 10 ₂, fed with a clockfrom a neighboring point set B-G, rises after a delay time correspondingto a delay time (a−b) to the neighboring point B plus (preset delay timeCons)+(2b/2) and rises after Cons+a as from the clock rising edge timepoint at the point A. An output J of a timing averaging circuit 10 ₃ andan output i of a timing averaging circuit 10 ₄ rise after time Cons=a asfrom the time point of the clock falling edge at point A, with thetimings of the rising edges of the signals I, J, K and L thus beingcoincident with one another.

[0078]FIGS. 3 and 4 illustrate the principle of the timing averagingcircuit 10 according to an embodiment of the present invention.Meanwhile, the timing averaging circuit 10 is a timing differencedividing circuit (interpolator) for outputting a signal corresponding tothe delay time obtained on interior division of a timing difference oftwo input signals by a preset ratio a, wherein the ratio of the interiordivision is set to 0.5 to make equal division of the timing difference.It is noted that the timing averaging circuit shown in FIG. 1 isconstituted by the timing difference division circuit.

[0079] Referring to FIG. 3a, the timing difference division circuit(TMD) includes inverters INV1, INV2, inverting and outputting inputsignals IN1, IN2, and p-channel MOS transistors MP1, MP2 having itssource, gate and drain connected to a power source VCC, outputs of theinverters IN1, IN2 and to an internal node N1, respectively. The timingdifference division circuit (TMD) also includes a buffer circuit BUFwhich has its internal node N1 connected to an input end and a logicaloutput value of which is changed when the potential of the internal nodeN1 is higher or lower than a threshold voltage, and a NOR circuit NOR1fed with input signals IN1, IN2 to output the results of NOR operations.The timing difference division circuit (TMD) also includes an N-channelMOS transistor MN1 having its drain, source and gate connected to theinternal node N1, ground potential GND and to the output end of the NORcircuit NOR1, respectively and a capacitor C connected across theinternal node N1 and the ground GND.

[0080] The timing difference division circuit (TMD) is shown in a blockdiagram of FIG. 3b. It is noted that the timing averaging circuitoutputs a signal corresponding to the delay time obtained on averagingthe timing difference of an input signal, with the ratio of the interiordivision of the timing averaging circuit being set to 0.5.

[0081]FIG. 4c shows three timing difference division circuits (TMDs), ofwhich a first timing difference division circuit (TMD) has its twoinputs fed with the same input signal IN1 to issue an output signalOUT1. A second timing difference division circuit (TMD) is fed with theinput signals IN1, IN2 to issue an output signal OUT2, whilst a thirdtiming difference division circuit (TMD) has its two inputs fed with thesame input signals IN1, IN2 to issue an output signal OUT2. Of thesethree timing difference division circuits (TMDs), the second timingdifference division circuit (TMD), fed with the input signals IN1, IN2to output the output signal OUT2, has a structure shown in FIG. 3a. Asfor the circuit structure having the first to third timing differencedivision circuits (TMDs), shown in FIG. 4C, reference should be made to,for example, a structure shown in FIG. 13a.

[0082] Referring to FIG. 4d, there is a timing difference T between theinput signals IN1, IN2, with the first, third and second timingdifference division circuits (TMDs) issuing an output signal OUT1 withdelay time t1, an output signal OUT3 with delay time t3 and an outputsignal OUT2 with delay time t2, respectively. The delay time t2 isobtained on interiorly dividing the delay time t1 and the delay time t3.

[0083] Referring again to FIG. 3a, when the input signals IN1, IN2 arelow, an output of the NOR circuit NOR1 goes high, with the N-channel MOStransistor MN1 being fired, the node N1 being at a ground potential andwith an output of the buffer circuit BUF going low.

[0084] If, with the threshold voltage V of an output of the buffercircuit BUF being inverted to the high level, the same input signals IN1are fed to the two input terminals IN1, IN2, the outputs of theinverters IN1, IN2 are low, both the p-channel MOS transistors MP1, MP2being fired, and the N-channel MOS transistor MN1 being turned off, withthe node N1 being charged with drain currents i1, i2. If charges of thenode N1, that needs to be charged up to a point of reaching thethreshold value of the buffer circuit BUF is CV, where C and V denotethe capacitance and the voltage, respectively, the delay time t1 isgiven by

t1=CV/(i1+i2).

[0085] Referring to FIG. 3a, if the input signal IN1 and the inputsignal IN2, rising with the delay of time T from the input signal IN1,are fed to the two input terminals IN1, IN2, as shown in FIG. 4c, anoutput of the inverter INV1 goes low at the time of rising of the inputsignal IN1, so that only the p-channel MOS transistor MP1 is turned on,while the N-channel MOS transistor MN1 is turned off, with the node N1being charged with the drain current i1 or a time duration T (charge atN1 being i1T). As the input signal IN2 then goes high, an output of theinverter INV2 goes low, with the p-channel MOS transistors MP1, MP2being turned on, with the N-channel MOS transistor MN1 being turned off,so that the node N1 is charged with the drain currents i1+i2. If thecharge of the node N1 that needs to be charged up to a threshold valueof the buffer circuit BUF is CV, where C and V denote the capacitanceand the voltage, respectively, the delay time t2 is given by:

t2=T+(CV−i1T)/(i1+i2)=T+CV/(i1+i2)−i 1 T/(i1+i2)=T(i2/(i1+i2)+t 1.

[0086] If the drain currents i1, i2 of the p-channel MOS transistorsMP1, MP2 are equal to each other,

t2=(½)T+t1.

[0087] If, in FIG. 3a, the same input signals iN2, delayed by time Tfrom the input signal IN1, is fed to the two input terminals IN1, In2,

t3=T+CV/(i1+i2).

[0088] Thus, by charging the capacitance of the internal node N1 of thetiming averaging circuit shown in FIG. 3a during the time Tcorresponding to the timing difference of the two input clocks, by thep-channel MOS transistor MP1 fed with the input signal IN1, and bycharging the capacitance by the p-channel MOS transistor MP2 fed withthe input signal IN2 and by the two p-channel MOS transistors, a timedifference of T/2, as an average value of the timing difference T of theinput signals IN1 and IN2, is produced from the time t1 as compared to acase where the same input signal IN1 is input from the outset forcharging by the two p-channel MOS transistors MP1, MP2.

[0089] So, the timing difference division circuit is termed “a timingaveraging circuit”.

[0090] According to an aspect of the present invention, without using aPLL circuit and a DLL circuit, the delayed time difference in the clockpath 11 can be suppressed low.

[0091] If, in the timing averaging circuit, the timing differencebetween the clock which undergoes transition first and the clock whichundergoes transition later is to be divided by a factor of ½ to output asignal with an averaged timing difference, this is accomplished byequating the on-currents (drain currents) i1, i2 of the p-channel MOStransistors MP1, MP2 of FIG. 3a. It is noted that, by setting the ratioof the on-currents (drain currents) i1, i2 of the p-channel MOStransistors MP1, MP2 of FIG. 3a to, for example, m:1, where m>1, anoutput signal having a delay time corresponding to the division of thetiming difference T of two clocks by an optional interior divisionratio. According to the present invention, this sort of the timingdifference division circuit may be used as a timing averaging circuitfed with two clocks at two points on the forward and return routes ofthe clock propagation path. By so doing, such a case in which the delaytime between a first time on the forward route and the reversing pointis not equal to the delay time between the reversing point and a secondposition on the return route can be coped with to realize phase matchingof respective clocks output by the timing difference dividing circuit.

[0092]FIG. 5 shows a configuration of a second embodiment of the presentinvention. In this second embodiment, the clock path 11 is functionally“circular”, with a direction-reversing point serving as a beginningpoint of the clock route (i.e., return route). An output of the inputbuffer 12 is fed to a branched point on a clock propagation path betweena route A, B, C and D and a route E, F, G and H. Two clock signals atcorresponding points (i.e., pairing points) A and H forming aneighboring point pair are input to the timing averaging circuit 10 ₁ tooutput an output signal L corresponding to the average delay time of twotiming differences. Two clock signals at corresponding points B and Gare input to the timing averaging circuit 10 ₂ to output an outputsignal K corresponding to the average delay time of two timingdifferences. Two clock signals at corresponding points C and F are inputto the timing averaging circuit 10 ₃ to output an output signal Jcorresponding to the average delay time of two timing differences.Similarly, two clock signals at points D and E are input to the timingaveraging circuit 10 ₄ to output an output signal I corresponding to theaverage delay time of two timing differences.

[0093] It should be noted that in the embodiment shown in FIG. 5, twobranched routes intersect each other at the reversing point. However,these branched routes may extend in parallel (specifically,anti-parallel) each other without intersection, which configurationprovides also the same advantage. The formulation shown in FIG. 5 hasbenefit of symmetrical arrangement of the clock path (routes) withrespect to a symmetry line connecting the input point (branching point)and the intersecting point.S

[0094] In the above-described embodiment (first embodiment) describedwith reference to FIG. 1, plural timing averaging circuits 10 ₁ to 10 ₄are arranged along forward and return routes 11 ₁, 11 ₂ of the clockpropagation path basically extending in a unidirectional direction. Inthe present second embodiment, there are provided forward and returnroutes 11 _(A), 11 _(D) of the clock propagation path, arranged at adistance from each other, and plural timing averaging circuits 10 ₁ to10 ₄ arranged for extending along the rims of forward and return routes11 _(A) and 11 _(D), for enlarging an area which allows for arraying ofthe timing averaging circuit within a chip.

[0095] In the second embodiment of the present invention, the timingaveraging circuit 10 may be configured as shown for example in FIGS. 6to 8. The timing averaging circuit 10, shown in FIGS. 6 to 8, averagesthe rising and falling timings of the clock signals. The timingaveraging circuit, shown in FIG. 3a, is configured for outputting arising signal prescribed by the delay time obtained on equally dividingthe timing difference of the rising edges of the two clock signals. Thetiming averaging circuit shown in any of FIGS. 6 to 8 may be appliedwith advantage to a configuration of furnishing clocks to a circuitadapted for operating using both rising and falling edges.

[0096] The timing averaging circuit, shown in FIG. 6, is now explained.

[0097] Referring to FIG. 6, the timing averaging circuit includes ap-channel MOS transistor MP51, having its source connected to a sourceVCC, a p-channel MOS transistor MP2 having its source connected to adrain of the p-channel MOS transistor MP1, an n-channel MOS transistorMN51, having its drain connected to the drain of the p-channel MOStransistor MP2, and an n-channel MOS transistor MN52, having its drainconnected to the source of the n-channel MOS transistor MN51 and itssource connected to the ground potential, with the input IN1 beingconnected in common to the gates of the p-channel MOS transistor MP1,MP2 and the n-channel MOS transistors MN51, MN52.

[0098] The timing averaging circuit includes a p-channel MOS transistorMP53, having its source connected to a source VCC, a p-channel MOStransistor MP54 having its source connected to a drain of the p-channelMOS transistor MP53, an n-channel MOS transistor MN53, having its drainconnected to the drain of the p-channel MOS transistor MP54, and ann-channel MOS transistor MN54, having its drain connected to the sourceof the n-channel MOS transistor MN53 and its source connected to theground potential, with the input IN1 being connected in common to thegates of the p-channel MOS transistor MP53 and to the n-channel MOStransistor MN54 and with the input IN2 being connected in common to thegates of the p-channel MOS transistor MP54 and the n-channel MOStransistor MN53.

[0099] The timing averaging circuit also includes a p-channel MOStransistor MP55, having its source connected to the source VCC, ap-channel MOS transistor MP56 having its source connected to a drain ofthe p-channel MOS transistor MP55 and having its drain connected to thesource VCC, a n-channel MOS transistor MN56, having its source connectedto the drain of the n-channel MOS transistor MN56, having its sourceconnected to the drain of the n-channel MOS transistor MN56 and havingits drain connected to the ground, with the input IN2 being connected tothe gates of the p-channel MOS transistor MP55 and the n-channel MOStransistor MN56.

[0100] The junction points of the p-channel MOS transistor MP52 and then-channel MOS transistor MN51 is connected to an input end of theinverter INV5, while the junction points of the p-channel MOS transistorMP54 and the n-channel MOS transistor MN53 is connected to an input endof the inverter INV5, an output end of which is connected to an outputterminal OUT.

[0101] The p-channel MOS transistors MP55, MP66 and the n-channel MOStransistors MN55, MN56 are connected to an input end of the inverterINV5, an output of which is connected to the output terminal OUT.

[0102] The operation of the timing averaging circuit shown in FIG. 6 isexplained. When the input signal IN1 rises from the low level to thehigh level, static charges of the node M51 are discharged from the pathsof the n-channel MOS transistors MN51, NM52. When the input signal IN2rises after a time delay of T from the low level to the high level aftera time delay of T, static charges of the node N51 are discharged fromthe n-channel MOS transistors of the two paths of the n-channel MOStransistors (n-channel MOS transistors MN51, NM52 and the n-channel MOStransistors MN53, NM54) so that a rising signal corresponding to thedelay time obtained on averaging the timing difference T of the inputsignals IN1 and IN2 is output as an output signal, as described above.

[0103] When the input signal IN1 decays from the high level to the lowlevel, the node 51 is charged from the path of the p-channel MOStransistors MP51, MP52 in the on state. When the input signal IN2 decayswith a delay of time T, the node N51 is charged through the p-channelMOS transistors of the two paths (p-channel MOS transistors MN51, NM52and the n-channel MOS transistors MN53, NM54) so that a decaying signalcorresponding to the delay time equal to the averaged timing differenceT between the input signals IN1, IN2 is output.

[0104] Since the input sequence of clocks IN1, IN2 is fixed in thetiming averaging circuit shown in FIG. 6, it is necessary to connect apoint at which a signal arrives first to a point at which a signal needsto be input first (IN1 of FIG. 6), in consideration of the arrangementof the clock path.

[0105] That is, if the timing averaging circuit shown in FIG. 6 is to beused for a timing averaging circuit 10 ₁ of FIG. 5, a point A at which asignal arrives first is an input end IN1, and a point H at which thesignal arrives with a time delay is connected to the input end IN2.

[0106] The reason is that, in the circuit configuration shown in FIG. 6,the number of transistors turned on and off by the inputs IN1, IN2 inthe charging/discharging path is not symmetrical. For example, in twocurrent paths across the source VCC and the internal node 52, (that isin the current paths of transistors MP51, MP52 and transistors MP53,MP54), the number of transistors turned on with the decaying of theinput IN1 is three (MP51, MP52 and MP53, of which MP51 and MP3 operateas a constant current source), whereas the number of the transistorsturned on with the decaying of the input IN2 is one (MP54), thustestifying to the non-symmetrical configuration with respect to theinputs IN1, IN2. In contrast with the timing averaging circuit of FIGS.7 and 8, explained next, the circuit configuration shown in FIG. 6 isnot provided with logical circuits for on/off control of a constantcurrent source transistor, so that the number of transistors can bediminished correspondingly.

[0107]FIG. 7 shows the configuration of another embodiment of the timingaveraging circuit according to the present invention. The timingaveraging circuit, shown in FIG. 7, can be used even in a case whereinthe clock inputting sequence is not determined at the outset. Moreover,inner transistors of NAND and NOR are used as parallel MOS transistors.

[0108] This timing averaging circuit, shown in FIG. 7, includes a NANDcircuit NAND61, having the inputs IN1, IN2 as inputs, inverter circuitsINV61, INV62 having the inputs IN1, IN2 as inputs, a p-channel MOStransistor MP61, having its source connected to the source VCC and alsohaving its gate connected to an output end of the NAND circuits NAND61.The timing averaging circuit also includes an n-channel MOS transistorMN61, having its drain connected to the drain of the p-channel MOStransistor MP61 and having its gate connected to the output end of theinverter circuit INV61, and an n-channel MOS transistor MN62, having itsdrain connected to the source of the p-channel MOS transistor MP61 andhaving its source connected to the ground. The timing averaging circuitalso includes an n-channel MOS transistor MN63 having its drainconnected to the drain of the p-channel MOS transistor MP61 and havingits gate connected to the output end of the inverter INV62, and ann-channel MOS transistor MN64 having its drain connected to the sourceof the n-channel MOS transistor MN63, and also having its source and thegate grounded and connected to the gate of the n-channel MOS transistorMN62, respectively.

[0109] The timing averaging circuit also includes a p-channel MOStransistors MP62, MP63, each having its source connected to the powersource VCC and having its gate connected together, and p-channel MOStransistors MP64, MP65, each having its source connected to the drainsof the p-channel MOS transistors MP62, MP63, and each having its gateconnected to output ends of the inverter circuits INV64, INV63 fed withthe inputs IN1, IN2, and an n-channel MOS transistor MN65 having itsdrain connected to the drains of the p-channel MOS transistors MP64,MP65 and having its gate connected to the output end of the NOR circuitNOR61 fed with the inputs IN1, IN2. The gates of the p-channel MOStransistors MP62, MP63 are connected in common to the gates of then-channel MOS transistors MN62, MN64.

[0110] The drain of the p-channel MOS transistor MP61 is connected tothe gate of the p-channel MOS transistor MP66, the source of which isconnected to the power source, while the drain of the p-channel MOStransistor MP66 is connected to the drain of the n-channel MOStransistor MN66, with the gate of the n-channel MOS transistor MN66being connected to the drain of the n-channel MOS transistor MN65, withthe source of the n-channel MOS transistor MN66 being grounded.

[0111] The junction point of the p-channel MOS transistor MP66 and then-channel MOS transistor MN66 is connected to the output terminal OUTthrough an inverter INV65, with an output of the inverter INV65 beingconnected through inverters INV66, INV67 to the common gate of then-channel MOS transistors MN62, MN64 and to the common gates of thep-channel MOS transistors MP62, MP63.

[0112] The operation of the timing averaging circuit shown in FIG. 7 isexplained.

[0113] In FIG. 7, when the input signals IN1, IN2 decay to the low levelfrom the high level, an output terminal of the NAND circuit NAND 61transits from the low level to the high level to turn the p-channel MOStransistor MP61 off, while turning on one and then both of the n-channelMOS transistors MN61, 63, the gates of which are fed with outputs of theinverters INV61, INV62. Since the output OUT is as yet at a high level,prior to decaying, the output potential OUT is transmitted through theinverters INV67, INV66 to the node N74, so that the node N74 goes high.Since the n-channel MOS transistors MN62, 64, the gate input of each ofwhich is the node N74, are turned on, the node N71 is discharged, thepotential of the node N71 is lowered to turn on the p-channel MOStransistor MP66. The potential of the node 73 goes high so that adecaying signal from the high level to the low level is output throughthe inverter INV65. The output signal OUT has a delay time correspondingto the delay time equal to one half of the timing difference between theinput signals IN1, IN2. The output potential OUT of the inverter INV65is transmitted through the inverters INV67, INV66 to the node N74. Whenthe output potential OUT goes low, the n-channel MOS transistors MN62,64 are turned off to turn on the p-channel MOS transistors MP62, MP63.

[0114] The timing averaging circuit shown in FIG. 7 includes the NANDcircuit NAND 61, and logical circuits in the form of the invertersINV61, INV62, and outputs a signal of a delay time corresponding to theaveraged timing difference between the input signals IN1, IN2, no matterwhich of the signals IN1, IN2 is advanced in phase relative to theother. (The averaged timing difference between the input signals IN1,IN2 is the average delay time between an output when an input is one ofthe input signals IN1 and IN2 which leads the other in phase and anoutput when an input is one of the input signals IN1 and IN2 which lagsthe other in phase.)

[0115] Referring to FIG. 7, when the input signals IN1, IN2 rise fromthe low level to the high level, an output of NOR circuit NOR61 decaysfrom the high level to the low level to turn off the n-channel MOStransistor MN65 as well as to turn on one and then both of the p-channelMOS transistors MP64, MP65, the gates of which are fed with outputs ofthe inverters INV63, INV64. Since the output OUT is as yet at a lowlevel, prior to rising, the output potential OUT is transmitted throughthe inverters INV66, INV67 to the node N74 to set the node N74 to a lowlevel to turn on the n-channel MOS transistors MN62, MN63 having thenode N74 as the gate input. This charges the node N72 to the low levelto raise its potential to turn on the n-channel MOS transistor MN66. Thenode N73 goes low so that a rising signal from the low level to the highlevel is output through the inverter INV65. As aforesaid, the outputsignal OUT has a delay time corresponding to one-half the timingdifference between the input signals IN1, IN2. The output potential OUTof the inverter INV65 is transmitted through the inverters INV66, INV67to the node N74. When the output potential OUT goes high, the n-channelMOS transistors MN62, MN63 are turned on, while the p-channel MOStransistors MP62, MP63 are turned off.

[0116] The timing averaging circuit shown in FIG. 7 also includes a NORcircuit NOR61, and logical circuits in the form of the inverters INV63,INV64, and outputs a signal of a delay time corresponding to theaveraged timing difference between the input signals IN1, IN2, no matterwhich of the signals IN1, IN2 is advanced in phase relative to theother. (The averaged timing difference between the input signals IN1,IN2 is the average delay time between an output when an input is one ofthe input signals IN1 and IN2 which leads the other in phase and anoutput when an input is one of the input signals IN1 and IN2 which lagsthe other in phase.) The timing averaging circuit shown in FIG. 7acquires control signals (gate signals) for turning on/off the n-channelMOS transistors MN62, MN64 and p-channel MOS transistors MP62, MP63,operating as the constant current source for charging/discharging theinternal nodes N71, N72, from the logical value of the output signalOUT. The present invention is, however, not limited to this feedbackconfiguration, and may be appropriately modified, provided that, indischarging the internal node N71, based on the first and second inputsignals IN1, IN2, the n-channel MOS transistors MN62, MN64 operating asthe constant current source are turned on, and that, in charging theinternal node N72, the p-channel MOS transistors MP62, MP63 operating asthe constant current source are turned on.

[0117]FIG. 8 shows an exemplary modification of the timing averagingcircuit shown in FIG. 7. This timing averaging circuit, shown in FIG. 8,includes a NAND circuit NAND71, having the inputs IN1, IN2 as inputs,inverter circuits INV61, INV62 having the inputs IN1, IN2 as inputs, ap-channel MOS transistor MP71, having its source connected to the sourceVCC and also having its gate connected to an output end of the inverterINV72. The timing averaging circuit also includes an n-channel MOStransistor MN73, having its drain connected to the drain of thep-channel MOS transistor MP71 and having its gate connected to theoutput end of the inverter circuit INV72, and an n-channel MOStransistor MN74, having its drain connected to the source of thep-channel MOS transistor MP73 and having its source and gate connectedto the ground and to the gate of the n-channel MOS transistor MN72.

[0118] The timing averaging circuit also includes a p-channel MOStransistors MP72, MP73, each having its source connected to the powersource VCC and having its gates connected together, and p-channel MOStransistors MP74, MP75, each having its source connected to the drainsof the p-channel MOS transistors MP72, MP73, and each having its gateconnected to output ends of the inverter circuits INV74, INV73 fed withthe inputs IN1, IN2, and an n-channel MOS transistor MN75 having itsrain connected to the drains of the p-channel MOS transistors MP74, MP75and having its gate connected to the output end of the NOR circuit NOR71fed with the inputs IN1, IN2. The gates of the p-channel MOS transistorsMP74, MP75 are connected in common to the gates of the n-channel MOStransistors MN72, MN73.

[0119] The drain of the p-channel MOS transistor MP71 is connected tothe gate of the p-channel MOS transistor MP76, the source of which isconnected to the power source, while the drain of the p-channel MOStransistor MP76 is connected to the drain of-the n-channel MOStransistor MN76, with the gate of the n-channel MOS transistor MN66being connected to the drain of the n-channel MOS transistor MN65, withthe source of the n-channel MOS transistor MN66 being grounded.

[0120] The junction point of the p-channel MOS transistor MP76 and then-channel MOS transistor MN76 is connected to the output terminal OUTthrough an inverter INV75.

[0121] The operation of the timing averaging circuit shown in FIG. 8 isexplained.

[0122] In FIG. 8, when the input signals IN1, IN2 decay to the low levelfrom the high level, an output terminal of the NAND circuit NAND 71transfers from the low level to the high level to turn the p-channel MOStransistor MP71 off, while turning on one and then both of the n-channelMOS transistors MN71, 73, the gates of which are fed with outputs of theinverters INV71, INV72. The node N81 is discharged, the potential of thenode N81 is lowered to turn on the p-channel MOS transistor MP76. Thepotential of the node 83 goes high so that a rising signal from the lowlevel to the high level is output through the inverter INV75. The outputsignal OUT has a delay time corresponding to the delay time equal to onehalf the timing difference between the input signals IN1, IN2.

[0123] Referring to FIG. 8, when the input signals IN1, IN2 rise fromthe low level to the high level, an output of NOR circuit NOR71 decaysfrom the high level to the low level to turn off the n-channel MOStransistor MN65 as well as to turn on one and then both of the p-channelMOS transistors MP74, MP75, the gates of which are fed with outputs ofthe inverters INV63, INV64. The node N82 is charged to the high level toraise its potential to turn on the n-channel MOS transistor MN76. Thenode N83 goes low so that a decaying signal from the high level to thelow level is output through the inverter INV75. As aforesaid, the outputsignal OUT has a delay time corresponding to one-half the timingdifference between the input signals IN1, IN2.

[0124] Referring to FIGS. 9 to 13, a third embodiment of the presentinvention is explained. This embodiment renders it possible to apply thepresent invention to a configuration in which the delay on the clockpropagation path is longer than the clock period tCK. Recently, with thetendency towards more variegated functions of the semiconductorintegrated circuit, the length of the clock propagation path tends to beincreased, while the operating frequency is becoming higher. Thus, if,in the configuration of the above-described embodiment shown for examplein FIG. 1, the delay quantity on the clock propagation path is longerthan the clock period tCK, for example, if the delay time 2a between apoint A on the forward route 11 ₁ remotest from the reversing point 11 ₃on the clock propagation path and a point H on the return route 11 ₂ islonger than the clock period tCK, the following results. That is, in thetiming averaging circuit 10 ₁, to the fist and second inputs which areinput clocks from the points A and H, there is input, before a clockinput to the clock propagation path reaches the point H to be input tothe second input end, the clock of the next following clock cycle isinput to the point A, such that a desired average value cannot beoutput. The present third embodiment of the present invention renders itpossible to realize the desired operation when the delay on the clockpropagation path is longer than the clock period tCK.

[0125] Referring to FIG. 9, clocks from frequency division by afrequency dividing circuit 14 from the input buffer 12 are fed to theclock propagation path (forward route 11 ₁, reversing point 11 ₃ andreturn route 11 ₂).

[0126] The clock signals from the input buffer 12 with a clock periodtCK, are frequency-divided by a frequency dividing circuit 14. Theclocks input to the clock propagation path 11 are turned on the clockpropagation path, with two clock signals at points A and H being fed tothe timing averaging circuit 10 ₁. An output signal L with the delaytime corresponding to a mean value of two timing differences is input toa multiplication circuit 15 ₁ which then outputs a multiplied signal P.Two clock signals at points B and G are fed to the timing averagingcircuit 10 ₂ which then outputs an output signal K with a delay timecorresponding to a mean value of the two timing differences to amultiplication circuit 15 ₂ to output a signal O. Two clock signals atpoints C and F are fed to a timing averaging circuit 10 ₃ which thenoutputs an output signal J with a delay time corresponding to a meanvalue of the two timing differences to a multiplication circuit 15 ₃ tooutput a multiplied signal N. Two clock signals at points D and E arefed to a timing averaging circuit 10 ₄ which then outputs an outputsignal I with a delay time corresponding to a mean value of the twotiming differences to a multiplication circuit 15 ₁ to output a signalM.

[0127]FIG. 10 shows a timing chart of the circuit shown in FIG. 9. Theclocks are frequency-divided by the frequency dividing circuit 14 andthe frequency divided clocks are sent to the clock propagation path 11on which the clocks are turned and sent over a bi-directional clocktransmission line. A mean value of the timings of the clock pulses istaken by the timing averaging circuit 10, an output of which ismultiplied by the multiplication circuit 15 to output a multipliedoutput.

[0128] According to the present invention, the multiplication circuit isrealized by the combination of timing averaging circuits. Thismultiplication circuit may be such a configuration proposed by thepresent inventors in JP Patent Applications JP-H-09-157042 (nowJP-A-11-004148) and JP-H-09-157028 (now JP-A-11-004145).

[0129] In the present embodiment, the delay magnitudes of the clockpropagation path can be matched solely by the timing averaging circuit,without using a feedback circuit, if the delay magnitude on the clockpropagation path 11 is longer than the clock period tCK.

[0130] Referring to FIGS. 11 to 15, an exemplary configuration of themultiplication circuit 15 embodying the present invention is explained.Referring to FIG. 11, in this multiplication circuit is the clock oncefrequency divided to give multi-phase clocks, and the timings among twoconsecutive phases of the multi-phase clocks are averaged to produce anew clock by way of timing averaging. Thus, the clock multiplicationcircuit uses this new clock output and a clock of a non-averaged outputto double the number of phases, followed by synthesizing these clocks toperform clock multiplication.

[0131] In more detail, referring to FIG. 11, the multiplication circuit15 includes a frequency dividing circuit 2 for frequency dividing clocks1 (in an preferred embodiment of the present invention, an output of thetiming difference averaging circuit) to generate multi-phase clocks 3, amulti-phase clock multiplication circuit 5, fed with outputs 3 of thefrequency dividing circuit 2, a period detection circuit 6 made up of afixed number of stages of ring oscillators and a counter for countingthe number of oscillations of the ring oscillator during one clockperiod to detect the clock period and a clock synthesis circuit 8 forsynthesizing outputs the multi-phase clock multiplication circuit 5 togenerate multiplied clocks 9. The multi-phase clock multiplicationcircuit 5 includes plural timing difference dividing circuits 4 a foroutputting a signal corresponding to the interior division of timingdifferences of two input signals and plural multiplication circuits 4 bfor multiplying outputs of two timing difference dividing circuits.

[0132] The plural timing difference dividing circuits 4 a comprisetiming difference dividing circuits each fed with the same phase clocksand with a timing difference dividing circuits each fed with twoneighboring clocks. The period detection circuit 6 outputs a controlsignal 7 to adjust the load capacity of the timing difference dividingcircuits 4 a in the multi-phase clock multiplication circuit 5 tocontrol the clock period.

[0133]FIG. 12 shows a specified configuration of a multiplicationcircuit for generating four-phase clocks as illustration of themultiplication circuit 15. Referring to FIG. 12, the multiplicationcircuit includes a ¼ frequency dividing circuit 201 for dividing thefrequency of the input clocks 204 by four for outputting four-phaseclocks Q1 to Q4, n series-connected four-phase clock multiplicationcircuits 202 ₁ to 202 _(n), a clock synthesis circuit 203 and a perioddetection circuit 204. The final-stage four-phase clock multiplicationcircuit 202 _(n) outputs 2n-multiplied four-phase clocks Qn1 to Qn4which are synthesized by the clock synthesis circuit 203 to outputfrequency multiplied clocks 207. Meanwhile, the number of stages of thefour-phase clock multiplication circuits is arbitrary.

[0134] A ¼ frequency dividing circuit 201 divides input clocks 205 by ¼to generate four-phase clocks Q1, Q2, Q3 and Q4, which then aremultiplied by the four-phase clock multiplication circuit 202 ₁ togenerate four-phase clocks Q11 to Q14. Similarly, 2n-multipliedfour-phase clocks Qn1 to Qn4 are produced from the four-phase clockmultiplication circuit 202 _(n).

[0135] The period detection circuit 204 is made up of a fixed number ofstages of ring oscillators, and a counter. During one period of theclocks, the period detection circuit 204 counts the number ofoscillations of the ring oscillators to output a control signal 206according to the number of counts to adjust the load in the four-phaseclock multiplication circuit 202. This period detection circuit 204eliminates variations in the operating range of clock periods and devicecharacteristics.

[0136] The four-phase clocks are rendered into eight phase clocks by thefour-phase clock multiplication circuit 202 and again rendered back intofour phase clocks for continuous frequency multiplication.

[0137]FIG. 13 shows an illustrative structure of the four-phase clockmultiplication circuit 202 _(n). It is noted that the four-phase clockmultiplication circuits 202 ₁ to 202 _(n) shown in FIG. 12 are all ofthe same structure.

[0138] Referring to FIG. 13a, this four-phase clock multiplicationcircuit 202 _(n) is made up of eight timing difference dividing circuits208 to 215, eight pulse width correction circuits 216 to 23 and fourmultiplication circuits 224 to 227. FIG. 13b shows the structure of apulse width correction circuit comprised of a NAND circuit fed with asignal comprised of a second input T23 inverted by the inverter IN2 andwith the first input T21 as inputs.

[0139]FIG. 13c shows a structure of a multiplexing circuit comprised ofa 2-input NAND circuit.

[0140]FIG. 14 shows a signal waveform diagram for illustrating thetiming operation of the four-phase clock multiplication circuits 202.The rising of the clock T21 is determined by the delay corresponding tothe internal delay of the timing difference dividing circuit 208, therising of the clock t22 is determined by the timing division by thetiming difference dividing circuit 209 of the rising timing of the clockQ(n−1) 1 and the rising of the clock Q(n−1) 2 and the delay caused bythe internal delay, and the rising of the clock T23 is determined by thetiming division by the timing difference dividing circuit 209 of therising timing of the clock Q(n−1) 1 and the rising of the clock Q(n−1) 2and the delay caused by the internal delay. In similar manner, therising of the clock t26 is determined by the timing division by thetiming difference dividing circuit 213 of the rising timing of the clockQ(n−1) 3 and the rising of the clock Q(n−1) 4 and the delay caused bythe internal delay, and the rising of the clock T27 is determined by thetiming division by the timing difference dividing circuit 214 of therising timing of the clock Q(n−1) 4 and the rising of the clock Q(n−1) 1and the delay caused by the internal delay.

[0141] The clocks T21 and t23 are fed to the pulse width correctioncircuit 216 which then outputs a pulse P21 having a falling edgedetermined by the clocks T21 and a falling edge determined by the clockT23. By a similar sequence of operations, pulses P22 to P28 aregenerated, with the clocks P21 to P28 becoming 25% duty eight-phasepulses with dephasing of 45 degrees. The clock P25 dephased by 180degrees from the clock P21 undergoes demultiplication in amultiplication circuit 224 so as to be output as 25% duty clocks Qn1. Insimilar manner, clocks Qn2 to Qn4 are generated. The clocks Qn1 to Qn4become 50% duty four-phase pulses, dephased 90 degrees each. The periodsof the clocks Qn1 to Qn4 are multiplied in frequency by two as clocksQn1 to Qn4 are generated from the clocks Q(n−1) 1 to (n01) 4.

[0142]FIGS. 15a and 15 b show the show illustrative structures of timingdifference dividing circuits 208, 209 shown in FIG. 13. These circuitsare at the same configuration and differ as to whether two inputs arethe same signals or two neighboring signals are input. That is, thetiming difference dividing circuit 208 and the timing differencedividing circuit 209 are at the same configuration except that, in theformer, the same input Q(n−1) 1 is fed to a two-input NOR circuit NOR14,whereas, in the later, input Q(n−1) 1 and Q(n−1) 2 are fed to thetwo-input NOR circuit NOR14. The two-input NOR circuit NOR14 is made upof two p-channel MOS transistors connected in series across the powersource VCC and the output end and the gates of which are fed with theinput signals IN1, IN2 and two n-channel MOS transistors connected inparallel across the input end and the ground and the gates of which arefed with the input signals IN1, IN2.

[0143] An internal node N51 (N61) as an output node of the two-input NORcircuit NOR14 is connected to an input end of the inverter IN2 15.Across the internal node and the ground, there is connected a parallelcircuit of a circuit comprised of a series connection of a n-channel MOStransistor MN51 and a capacitance CAP51, a series connection of an-channel MOS transistor MN52 and a capacitance CAP52 and a seriesconnection of a n-channel MOS transistor MN53 and a capacitance CAP53.To the gates of the respective n-channel MOS transistors MN51 to 53 iscoupled the control signal 7 from the period detection circuit 6 to turnthe transistors on or off. The size ratio of the gate widths of then-channel MOS transistors MN51 to 53 to the capacitances CAP51 to 53 isset to, for example, 1:2:4. The load connected to the common node isadjusted in eight stages to set the clock period.

[0144] Turning to the timing difference dividing circuit 208, staticcharges of the node N51 are extracted through a n-channel MOS transistorof the NOR14. When the potential of the node N51 reaches the thresholdvalue of the inverter IN2 15, there rise clocks T21, as output of theinverter INV15. If the static charges of the node N51, that need to beextracted when the threshold value of the inverter INV15 is reached, aredenoted CV, where C and V denote the capacitance and the voltage,respectively, and the discharging current by the n-channel MOStransistor of the NOR14 is denoted I, the static charges of CV aredischarged with the current value 2I, as a result of which the timeCV/2I represents the timing difference (propagation delay time) as fromthe rising edge of the clock Q(n−1) 1 until the rising of the clock T21.When the clock Q(n−1) 1 is low, an output node N51 of the two-input NORcircuit NOR14 is charged to the high level, with the output clock T21 ofthe inverter INV15 being then at a low level.

[0145] As for the timing difference dividing circuit 209, static chargesof the node N61 are extracted by the NOR14 after time tCKn(tCKn=multi-phase clock period) from the rising edge of the clockQ(n−1). The edge of the clock T22 rises when, after time tCKn, thepotential of the node n61 reaches the threshold value of the inverterINV15 from the rising edge of the clock Q(n−1). If the static charges ofthe node N61 are denoted CV, and the discharge current of the n-MOStransistor of the two-input NOR circuit NOR14 is I, static charges CVare discharged from the rising of the clock Q(n−1) 1 with the current Iduring the time period tCKn, and extraction is made with the current 2Iduring the remaining period. So, the time

tCKn+(CV−tCKn I)/2I=CV/2I+tCKn/2

[0146] represents the timing difference of the rising edge of the clockT22 from the rising edge of the clock Q(n−1) 1.

[0147] That is, the rising timing difference between clocks T22 and T21is tCKn/2.

[0148] If the clock Q(n−1) 1 and the clock Q(n−1) 2 are both low and theoutput node N61 of the two-input NOR circuit NOR14 is charged through apMOS transistor of the NOR14 from the power source to a high level, theclock T22 rises. The same situation holds for the clocks T22 to T28,with the timing difference between the rising edges of the clocks T21 toT28 being tCKn/2.

[0149] The pulse width correction circuits 216 to 223 generate 25% duty8-phase pulses A23 to T28, dephased 45 degrees relative to one another.

[0150] The multiplexing circuits 224 to 227 generate 50% duty 4-phasepulses Qn1 to Qn4, dephased 45° relative to one another.

[0151] Referring to FIGS. 16 to 18, a fourth embodiment of the presentinvention is now explained. In the present embodiment, the presentinvention is applied to a configuration in which the delay magnitude onthe clock path is longer than the clock period tCK.

[0152] Referring to FIG. 16, showing the fourth embodiment of thepresent invention, clocks are first supplied to a direction-reversedbi-directional clock propagation path. In each neighboring point pair inthe forward route 11 ₁ and return route 11 ₁ are frequency divided intiming averaging circuits 100 ₁ to 100 ₄ provided with the frequencydividing function. The clock pulse timings of the frequency dividedclocks are averaged using the timing averaging circuits and subsequentlysynthesized by synthesis circuits 16 ₁ to 16 ₄. The clocks input to theclock propagation path 11 are direction-reversed on the clockpropagation path, such that two clock signals at points A and H are fedto the timing averaging circuit 100 ₁ provided with the frequencydividing function to generate output signals L1 to L4 with the delaytime corresponding to the mean value of two timing differences of thefrequency divided clocks, with the output signals L1 to L4 beingsynthesized by the synthesis circuit 16 ₁ to output a signal P.Similarly, two clock signals at points B and G are fed to the timingaveraging circuit 100 ₂ provided with the frequency dividing function togenerate output signals L1 to L4 with the delay time corresponding tothe mean value of two timing differences of the frequency dividedclocks, with the output signals K1 to K4 being synthesized by thesynthesis circuit 16 ₂ to output a signal O, and two clock signals atpoints C and F are fed to the timing averaging circuit 100 ₃ providedwith the frequency dividing function to generate output signals J1 to J4with the delay time corresponding to the mean value of two timingdifferences of the frequency divided clocks, with the output signals J1to J4 being synthesized by the synthesis circuit 16 ₃ to output a signalN, while two clock signals at points D and E are fed to the timingaveraging circuit 100 ₄ provided with the frequency dividing function togenerate output signals I1 to 14 with the delay time corresponding tothe mean value of two timing differences of the frequency dividedclocks, with the output signals I1 to I4 being synthesized by thesynthesis circuit 16 ₄ to output a signal M.

[0153]FIG. 17 shows the configuration of the timing averaging circuit100 ₁ provided with the frequency dividing function. The remainingtiming averaging circuits 100 ₂ to 100 ₄ provided with the frequencydividing function are configured in a similar fashion. The signals A1 toA4, obtained on frequency division of the clock at point A on the clockpropagation path 11 by a frequency dividing circuit 10 ₁ are sent totiming averaging circuit 102 ₁ to 102 ₄, while the signals B1 to B4,obtained on frequency division of the clock at point H on the clockpropagation path 11 by a frequency dividing circuit 101 ₂ are sent tothe timing averaging circuit 102 ₁ to 102 ₄. The timing averagingcircuit 102 ₁ outputs a median (mean) value signal L1 of the timingdifferences of A1 and B1, while the timing averaging circuit 102 ₂outputs a median value signal L2 of the timing differences of A2 and B2.In similar manner, the timing averaging circuit 102 ₄ outputs a medianvalue of the timing differences of A4 and B4, whilst the synthesiscircuits 16 synthesizes signals 11 to 14 to output a signal P.

[0154] Thus, in the present embodiment, the clocks of each point of theforward route 11 ₁ and the return route 11 ₁ of the clock propagationpath are frequency divided by four in the frequency dividing circuits101 ₁. 101 ₂ to generate four-phase clocks to generate four signalsobtained on averaging the timing differences of the two correspondingfrequency divided clocks in the timing averaging circuit, these foursignals being synthesized to one signal P by the synthesis circuit 16.Since the output of the synthesis circuit 16 is equivalent to themultiplexed output, the delay magnitude of the clock path can be matchedsolely by the timing averaging circuits 100 ₁ to 100 ₄ provided with thefrequency dividing function, without using the multiplexing circuit,even if the delay magnitude on the clock propagation path of thefrequency divided clocks is longer than the clock period. The circuitscale of the present embodiment not provided with the multiplexingcircuit is at a smaller circuit scale than the one of the thirdembodiment.

[0155]FIG. 18 shows a timing chart illustrating the operation of afourth embodiment of the present invention.

[0156] The frequency dividing circuits 101 ₁, 101 ₂ fed with signals atpoints A and H output signals A1 to A4 and B1 to B4 obtained onfrequency division by four, with the timing averaging circuit 102 ₁outputting a signal corresponding to a mean value of the timingdifferences of the signals A1 and B1, with the timing of thepost-synthesized output signals M to P being corresponding with oneanother.

[0157] Referring to FIGS. 19 and 20, a fifth embodiment of the presentinvention is explained. In the present embodiment the present inventionis applied to a configuration in which the delay magnitude on the clockpropagation path is longer than the clock period tCK.

[0158] Referring to FIG. 19, showing the fifth embodiment of the presentinvention, input clocks 13 are frequency divided by the frequencydividing circuit 14, and multi-phase (four-phase) clocks output by thefrequency dividing circuit 14 are output into clock wirings 11-1 to11-4. The clock wirings equal in number to the number of phases of theclocks are direction-reversed to serve as bi-directional clocktransmission lines. The timings of the clocks on the wirings of the eachphases are averaged, using the timing averaging circuit (TM), andsubsequently synthesized in the synthesis circuit 16.

[0159] The present fifth embodiment includes four timing averagingcircuits (TM), fed with signals on paired points A1 to A4 on the forwardroute and on paired points H1 to H4 on the return route of the sameclock propagation paths 11-1 to 11-4 to generate output signals L1 toL4, a synthesis circuit 16 ₁ for synthesizing the L1 to L4 to generatean output signal P, four timing averaging circuits (TM), fed withsignals on paired points B1 to B4 on the forward route and on pairedpoints G1 to G4 on the return route of the same clock propagation paths11-1 to 11-4 to generate output signals K1 to K4, a synthesis circuit 16₂ for synthesizing the K1 to K4 to generate an output signal O, fourtiming averaging circuits (TM), fed with signals on paired points C1 toC4 on the forward route and on paired points F1 to F4 on the returnroute of the same clock propagation paths 11-1 to 11-4 to generateoutput signals J1 to J4, a synthesis circuit 16 ₃ for synthesizing theJ1 to J4 to generate an output signal N, four timing averaging circuits(TM), fed with signals on paired points D1 to D4 on the forward routeand on paired points E1 to E4 on the return route of the same clockpropagation paths 11-1 to 11-4 to generate output signals I1 to I4, anda synthesis circuit 16 ₄ for synthesizing the I1 to 14 to generate anoutput signal M. In the present embodiment the outputs M to P arephase-matched relative to one another.

[0160] In the present embodiment, similarly to the above-describedfourth embodiment, the delay magnitude of the clock path can be matchedsolely by the timing averaging circuit, without using the multiplexingcircuit, in a case wherein the delay magnitude on the clock propagationpath is longer than the clock period. In the above-described fourthembodiment, the timing averaging circuits provided with the frequencydividing function are provided with two frequency dividing circuits. Inthe present embodiment, provided with the frequency dividing circuit 14for frequency dividing the input clocks 13 to furnish the resultingfrequency divided clocks to the four clock propagation paths 11-1 11-4,the delay magnitudes of the clock paths can be matched with a smallernumber of frequency dividing circuits. That is, although the number ofwirings for the clock propagation paths is increased, the circuit scalecan be reduced as compared to that in the fourth embodiment.

[0161] A sixth embodiment of the present invention is explained withreference to FIG. 21. The present sixth embodiment uses a timingaveraging circuit TM and two layers of the clock pulse timing averagingcircuits to furnish the clock propagation path in a mesh-like fashion.Referring to FIG. 21, timing averaging circuits 110 ₁ to 110 ₄ foraveraging the timings at preset points on the forward and return routesof the clock propagation path 111 adapted for propagating the clocksfrom the input buffer 112 are provided on one side of a chip. Aplurality of circuits for averaging the clock pulse timings, fed withoutputs of buffers 113 ₁ to 113 ₄, fed in urn with outputs of the timingaveraging circuit 110 ₁ to 110 ₄, are arranged in parallel from thewirings corresponding linearly in timing, and outputs are connected in ameshed fashion.

[0162] In the present sixth embodiment, clock signals can be supplied inwhich the delay magnitudes on the clock path are corresponding on theentire chip in a two-dimensional fashion in a semiconductor integratedcircuit. That is, the clock timing supplied to the clock-usingcircuitry, such as synchronization circuit, on the entire chip area canbe matched, no mater where the clock using circuitry is arranged on thechip layout surface.

[0163] In the timing averaging circuit of the sixth embodiment of thepresent invention, employing the circuit components similar to those ofthe fourth embodiment, it is possible to cope with a configuration inwhich the delay magnitude of the clock path is longer than the clockperiod.

[0164] According to the present invention, as described above, thephases of the clocks furnished in the internal circuit of thesemiconductor integrated circuit furnished with clocks can be matched inphase in a short time and is suitably used for clock synchronizationcontrol in a large-scale integrated circuit. Moreover, the presentinvention can be applied to clock control of a substrate or a variety ofdevices without being limited to the semiconductor integrated circuit.

[0165] The meritorious effects of the present invention are summarizedas follows.

[0166] According to the present invention, as described above, there maybe provided a circuit in which the wiring delay in a direction-reversedbi-directional clock propagation path to eliminate the delay differenceon the clock transmission line in its entirety, wherein the delaydifficult may be eliminated in a shorter time.

[0167] The reason is that the timing is corresponding using a timingaveraging circuit without using PLL or DLL to overcome the problem thata long clock cycle is needed until elimination of the delay difference.

[0168] According to the present invention, the circuit scale may beprevented from being increased.

[0169] The reason is that, in the present invention, phase comparatorsor concatenated delay circuits are eliminated in contradistinction fromthe conventional apparatus provided with plural phase comparators orplural concatenated delay circuits etc.

[0170] It should be noted that other objects, features and aspects ofthe present invention will become apparent in the entire disclosure andthat modifications may be done without departing the gist and scope ofthe present invention as disclosed herein and claimed as appendedherewith.

[0171] Also it should be noted that any combination of the disclosedand/or claimed elements, matters and/or items may fall under themodifications aforementioned.

1-5. (canceled)
 6. A clock controlling circuit comprising: a pluralityof timing averaging circuits each provided with a frequency dividingfunction for receiving first and second, frequency divided clocks,including the first clock from a first position on a forward route of aclock propagation path, adapted for being fed with input clocks at oneend and direction-reversing therein the input clocks, and the secondclock from a second position on a return route of said clock propagationpath according to said first position; and a synthesis circuit forsynthesizing plural outputs of said timing averaging circuits having afrequency dividing function into one signal; at least one of said timingaveraging circuits having first and second frequency dividing circuitsfor frequency dividing two clocks to output plural frequency dividedclocks having respective different phases. 7-34. (canceled)
 35. Theclock controlling circuit of claim 6, wherein at least one of saidtiming averaging circuits is configured to issue said output signal witha first delay time corresponding to a delay time until said outputsignal is issued after one of said two clocks undergoing transition atan earlier time point is input simultaneously to first and second inputsof said two clocks, added with a second delay time corresponding to atime obtained on equally dividing the timing difference T of said twoclocks (T/2).
 36. The clock controlling circuit of claim 6, wherein atleast one of said timing averaging circuits is arranged for charging ordischarging an internal node based on one of said two input clocksundergoing transition at an earlier time and for charging or dischargingsaid internal node based on the other clock undergoing transition with adelay time from said one clock, and on said one clock; and furthercomprising a buffer circuit connected to an input end thereof to saidinternal node and whose output logical value is changed when saidinternal node voltage exceeds or falls below a threshold voltage. 37.The clock controlling circuit of claim 6, wherein at least one of saidtiming averaging circuits comprises: first and second switch elementsconnected in parallel across a first power source and the internal nodefor being turned on and off when the first and second inputs are atfirst and second values, respectively; a third switch element connectedacross said internal node and a second power source, said third switchelement being fed with said first and second inputs and being turned onwhen said third switch element is at said second value; a capacitanceconnected across said internal node and said second power source; and abuffer circuit an output logical value of which is determined based onthe relative magnitudes of the potential of said internal node and athreshold value.
 38. The clock controlling circuit of claim 6, whereinat least one of said timing averaging circuits comprises: a plurality offirst switch elements each connected in series across a first powersource and an internal node, said first switch elements having controlterminals fed with a first input and being turned off when said firstinput is at a first value; a plurality of second switch elements eachconnected in series across said internal node and a second power source,each second switch element having its control terminal connected to saidfirst input and being turned on when said first input is at a firstvalue; a third switch element and a fourth switch element connected inseries across said first power source and said internal node, said thirdswitch element having its control terminal connected to said firstinput, and being turned off when said first input is at a first value,and said fourth switch element having its control terminal connected tosaid second input and being turned off when said second input is at afirst value; a fifth switch element and a sixth switch element connectedin series across said internal node and said second power source, saidfifth switch element having its control terminal connected to saidsecond input, and being turned on when said second input is at a firstvalue, and said sixth switch element having its control terminalconnected to said first input and being turned on when said first inputis at said first value; and an inverter circuit an output logical valueof which is determined based on relative magnitudes of said internalnode and a threshold value.
 39. The clock controlling circuit as definedin claim 38, wherein a switch element having its control terminalconnected to said first input is connected to said first power source, aswitch element having its control terminal connected to said secondinput is connected to said second power source, and wherein the numbersof the switch elements operating as loads for said first and secondinputs are equal to each other.
 40. The clock controlling circuit ofclaim 6, wherein at least one of said timing averaging circuitscomprises: a first switch element, connected across said first powersource and a first internal node; a first logical circuit fed with firstand second input signals and having its output end connected to acontrol terminal of said first switch element, said first switch elementbeing turned on when both said first and second input signals are at afirst value; a second switch element and a third switch elementconnected in series across said first internal node and the second powersource, said second switch element being turned off or on when saidfirst input signal is at said first or second value, respectively, saidthird switch element being turned on or off when the output signal is atsaid first or second value, respectively; a fourth switch element and afifth switch element connected in series across said first internal nodeand the second power source, said fourth switch element being turned offor on when said second input signal is at said first or second value,respectively, and said fifth switch element being turned on or off whenthe output signal is at said first or second value, respectively; asixth switch element connected across said first power source and athird internal node for inputting said first internal node to a controlterminal; a seventh switch element connected across said second powersource and a second internal node; a second logical circuit fed withfirst and second input signals and having its output end connected to acontrol terminal of said seventh switch element, said seventh switchelement being turned on when both said first and second input signalsare at a second value; an eighth switch element and a ninth switchelement connected in series across said second internal node and thefirst power source, said eighth switch element being turned on or offwhen said first input signal is at said first or second value,respectively, said ninth switch element being turned off or on when theoutput signal is at said first or second value, respectively; a tenthswitch element and an eleventh switch element connected in series acrosssaid second internal node and the first power source, said tenth switchelement being turned on or off when said second input signal is at saidfirst or second value, respectively, and said eleventh switch elementbeing turned off or on when said output signal is at said first orsecond value, respectively; a twelfth switch element connected acrosssaid second power source and said third internal node for inputting saidsecond internal node to a control terminal; and an inverter circuithaving its input terminal fed with said third internal node and anoutput logical value of which is determined by the relative magnitudesof said third internal node potential and a threshold value; and whereinthe clock control circuit further comprises: a circuit means foron/off—controlling a first switch element pair made up of said thirdswitch element and the fifth switch element and a second switch elementpair made up of said ninth switch element and the eleventh switchelement.
 41. The clock controlling circuit of claim 6, wherein at leastone of said timing averaging circuits comprises: a first switch elementconnected across said first power source and a first internal node; afirst logical circuit fed with first and second input signals and havingits output end connected to a control terminal of said first switchelement, said first switch element being turned on when both said firstand second input signals are at a first value; a second switch elementand a third switch element connected in series across said firstinternal node and the second power source, said second switch elementbeing turned off or on when said first input signal is at said first orsecond value, respectively, said third switch element being turned on oroff when the output signal is at said first or second value,respectively; a fourth switch element and a fifth switch elementconnected in series across said first internal node and the second powersource, said fourth switch element being turned off or on when saidsecond input signal is at said first or second value, respectively, saidfifth switch element being turned on or off when the output signal is atsaid first or second value, respectively; a sixth switch elementconnected across said first power source and a third internal node forinputting said first internal node to a control terminal; a seventhswitch element connected across said second power source and a secondinternal node; a second logical circuit fed with first and second inputsignals and having its output end connected to a control terminal ofsaid seventh switch element, said seventh switch element being turned onwhen both said first and second input signals are at a second value; aneighth switch element and a ninth switch element connected in seriesacross said second internal node and the first power source, said eighthswitch element being turned on or off when said first input signal is atsaid first or second value, respectively, said ninth switch elementbeing turned off or on when an output signal is at said first or secondvalue, respectively; a tenth switch element and an eleventh switchelement connected in series across said second internal node and thefirst power source, said tenth switch element being turned on and offwhen said second input signal is at said first or second value,respectively, said eleventh switch element being turned off or on whensaid output signal is at said first or second value, respectively; atwelfth switch element connected across said second power source andsaid third internal node for inputting said second internal node to acontrol terminal; and an inverter circuit having its input terminal fedwith said third internal node and an output logical value of which isdetermined by the relative magnitudes of said third internal nodepotential and a threshold value, wherein said output signal is issuedfrom an output end of said inverter circuit, and wherein an output of abuffer circuit generating a normal output of said output signal isconnected in common to control terminals of said third switch element,said fifth switch element, said ninth switch element and said eleventhswitch element.
 42. The clock controlling circuit of claim 6, wherein atleast one of said timing averaging circuits comprises: a first switchelement connected across said first power source and a first internalnode; a first logical circuit fed with first and second input signalsand having its output end connected to a control terminal of said firstswitch element, said first switch element being turned on when both saidfirst and second input signals are at a first value; second and thirdswitch elements connected in series across said first internal node anda second power source, said second switch element being turned off or onwhen said first input signal is at said first or second value,respectively; fourth and fifth switch elements connected in seriesacross said first internal node and second power source, said fourthswitch element being turned off or on when said second input signal isat said first or second value, respectively; a sixth switch elementconnected across said first power source and a third internal node forinputting said first internal node to a control terminal; a seventhswitch element connected across said second power source and a secondinternal node; a second logical circuit fed with first and second inputsignals and having its output end connected to a control terminal ofsaid seventh switch element, said seventh switch element being turned onwhen both said first and second input signals are at a second value;eighth and ninth switch elements connected in series across said secondinternal node and said first power source, said eighth switch elementbeing turned on or off when said first input signal is at said first orsecond value, respectively; tenth and eleventh switch elements connectedin series across said second internal node and said first power source,said tenth switch element being turned on or off when said second inputsignal is at said first or second value, respectively; and a twelfthswitch element connected across said second power source and said thirdinternal node for inputting said second internal node to a controlterminal; and an inverter circuit having its input terminal fed withsaid third internal node, and an output logical value of which isdetermined by the relative magnitudes of said third internal nodepotential and a threshold value; an output of said first logical circuitbeing connected to control terminals of said ninth and eleventh switchelements; an output of said second logical circuit being connected tocontrol terminals of said third and fifth switch elements.